The present invention regards a process for manufacturing electronic devices comprising nonvolatile memory cells of reduced dimensions.
Devices using nonvolatile memories, for example of the EPROM type or EEPROM type, such as smart cards, complex microcontrollers and mass storage devices which require programmability of the individual byte, call for increasingly higher levels of performance and reliability.
In practice, from the technological standpoint, this means that it is necessary to get high performances (i.e., increasingly thinner tunnel oxides, ever more reduced programming voltages, increasingly greater cell current-driving capability, etc.) to coexist with an extremely high reliability: one hundred thousand programming cycles and retention of the stored charge for at least ten years are by now considered the minimum requisites for accepting these products on the market.
Therefore, it is necessary to develop new manufacturing processes and new geometries that are able to eliminate some of the critical aspects typical of memories, thus increasing their intrinsic reliability without reducing their performance, both for xe2x80x9cembeddedxe2x80x9d applications (i.e., ones in which the memory cells are associated to electronic devices that perform preset functions) and for stand-alone applications (i.e., ones in which the device is merely a nonvolatile memory).
In particular, the reduction in the dimensions of memory devices entails severe constraints as regards formation of contacts and alignment of contacts with the drain regions.
For reducing the dimensions of memory devices, alternate metal ground (AMG) devices are known, wherein the diffused source lines and diffused drain lines are parallel, and the contacts are formed outside the area of the memory cells.
However, these memory devices have the problem that the word lines, formed by non-planar polysilicon strips defining the control gate regions of the memory cells, undergo sharp changes in direction in reduced spaces (corresponding to the width of the diffused source and drain lines). In addition, the polysilicon strips are not well insulated from the substrate because of the reduced thickness of the tunnel layer.
The present invention provides a manufacturing process that reduces the constraints with respect to the formation and alignment of the contacts of the memory cells, and hence reduces the dimensions of the memory cells without reducing their performance.
According to the present invention, a process for manufacturing electronic devices comprising nonvolatile memory cells, and an electronic device comprising nonvolatile memory cells are provided.
In accordance with one embodiment of the invention, a process for manufacturing electronic devices including memory cells is disclosed, including forming stacks on a substrate of semiconductor material, the stacks including a floating gate region of semiconductor material, an intermediate dielectric region, and a control gate region of semiconductor material; forming a protective layer of insulating material extending on top of the substrate and between the stacks, the protective layer having a height at least equal to that of the stacks; wherein forming the stack structures includes defining the control gate region in two non-parallel directions so that each control gate region is separate and electrically insulated with respect to the control gate regions belonging to adjacent stack structures; and such that, during the forming of the protective layer, the stack structures are completely isolated with respect to one another in the two directions, and further including forming word lines of conductive material that extend above the protective layer and that are in electrical contact with the control gate regions.
In accordance with another embodiment of the invention, a process for manufacturing electronic devices is disclosed that includes forming first insulating regions and second insulating regions in a first area and, respectively, in a second area separate from the first area, of a substrate of semiconductor material, the process including forming a hard mask having openings on the first area; forming trenches in the second area; depositing an insulating material layer filling the trenches and the openings; and selectively removing the insulating material layer on top of the hard mask and on top of the trenches so as to simultaneously form the first insulating regions and the second insulating regions; the first insulating regions in the first area having a different height from the second insulating regions in the second area.
In accordance with yet another aspect of the present invention, an electronic device is disclosed that includes a substrate of semiconductor material; memory cells, each including a stack on top of the substrate, each of the stacks comprising a floating gate region of semiconductor material, an intermediate dielectric region, and a control gate region of semiconductor material; and a protective layer extending on top of the substrate and between the stack structures, the protective layer having a height at least equal to that of the stack structures and word lines of conductive material extending on top of the insulating material layer; and further wherein the control gate region is physically separated from the control gate regions belonging to adjacent stack structures by the protective layer, and including word lines extending on top of the control gate regions and in electrical contact with the control gate regions.
In accordance with still yet another embodiment of the present invention, a process for manufacturing electronic devices on a substrate of semiconductor material is disclosed. This process includes forming a control gate region in two nonparallel directions on a stack formed of an intermediate dielectric region on top of a floating gate region; surrounding each stack with a protective layer of nonconductive material; and forming a word line of conducting material above the protective layer and in electrical contact with the control gate region.